Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field programmable systems on a chip (FPSCs), or other types of programmable devices) may be configured with various user designs to implement desired functionality. Typically, the user designs are synthesized and mapped into configurable resources (e.g., programmable logic gates, look-up tables (LUTs), embedded hardware, or other types of resources) and interconnections available in particular PLDs. Physical placement and routing for the synthesized and mapped user designs may then be determined to generate configuration data for the particular PLDs.
Each user design typically includes clock signals to coordinate operation of various components within the user design, and each PLD has a limited number of clock resources (e.g., clock driver input/output pins, feedline interconnects between such clock driver sources and other components of the PLD, and/or other PLD resources) to implement the user design. Conventional methods for physical placement of clock resources can take a relatively long time to complete and can fail without indicating whether a solution exists, and these problems are exacerbated as the number of available clock resources for PLDs becomes increasingly limited relative to the portion of the PLD dedicated to implementing other aspects (e.g., desired logic operations) of a user design. Moreover, such conventional methods may also be susceptible to inefficiently allocating clock resources, which can negatively impact other characteristics of the user design, such as achievable throughput or clock speed.
Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.